1. Technical Field
The present disclosure relates in general to a circuit for driving a load, and in particular to a circuit having low electromagnetic emissions, for example for use in automotive applications.
2. Description of the Related Art
In many electrical applications in the automotive industry, electrical components, such as lamps or heating coils, are powered using a pulse width modulated (PWM) signal, allowing the power levels to be controlled relatively precisely.
In such applications, there is a desire to minimize electromagnetic emissions, which may interfere with communications equipment such as radio receivers. For example, the CISPR 25 (International Special Committee on Radio Interference) standard introduces strict limits on permissible electromagnetic emissions.
In order to reduce electromagnetic emissions in sensitive frequency bands, the frequency of the PWM signal used for driving the electrical components is generally kept low, for example at between 50 and 400 Hz.
It has also been proposed to control, in a discrete fashion, the rise and fall of the power levels supplied to the electrical components at the rising and falling edges of a PWM signal.
FIGS. 1 and 2 reproduce FIGS. 13 and 12 respectively of patent publication US 2007/0103133.
FIG. 1 illustrates a circuit 100 comprising a lamp forming a load, which receives a voltage Ua supplied by voltage KL30 via a power switch S1. The gate of switch S1 is coupled via a switch 102 to a node 104, and via a switch 106 to a node 108. Node 104 is in turn coupled to a positive supply voltage +UH via the parallel connection of three fixed current sources I1, I2 and I3, wherein the branches of current sources I2 and I3 can be selectively activated by further switches. Similarly, node 108 is in turn coupled to a ground voltage via the parallel connection of a further three current sources I1′, I2′ and I3′, wherein the branches of current sources I2′ and I3′ can be selectively activated by further switches.
Three comparators Cmp1, Cmp2 and Cmp3 control the switches for activating the branches of current sources I2, I3, I2′ and I3′. Comparator Cmp1 compares the gate voltage Ug of the power switch S1 with a threshold voltage, while comparators Cmp2 and Cmp3 compare the output voltage Ua with corresponding threshold voltages. The outputs of comparators Cmp1 and Cmp2 are provided to an AND gate, the output of which controls the switches in the branches of current sources I3 and I3′, while the output of comparator Cmp3 controls the switches in the branches of current sources I2 and I2′.
FIG. 2 shows a timing diagram 202 illustrating a PWM signal over time, a timing diagram 204 illustrating the output voltage Ua as a percentage of the supply voltage Ubat, and a timing diagram 206 illustrating the resulting current supplied to the gate of switch S1.
Upon activation of the PWM signal as shown in timing diagram 202, the output voltage Ua initially stays low, and thus the three current sources I1, I2 and I3 are activated. Then, at a time t1, the output voltage Ua starts to increase, and the current is reduced to the value of just I1. When the output voltage reaches 10% of the supply voltage KL30, the second supply current I2 is activated, and when the voltage reaches 20% of the supply voltage KL30, all the current sources I1, I2 and I3 are activated. Then, when the output voltage reaches 80% of the supply voltage KL30, the current source 13 is disabled, and when the output voltage reaches 90% if the supply voltage KL30, the current is reduced to just that of current source I1. During the descent, the reverse control sequence is performed based on the current sources I1′, I2′ and I3′, which discharge the gate to ground.